The most widely used technology for interconnecting power semiconductor chips and connecting them to conductor tracks is thick-wire bonding. In this technique ultrasound energy is used to achieve a permanent connection between an Al wire, which has a typical diameter of several 100 μm, and the contact surface, which is an Al surface on the chip or Cu surface on the power module, via an intermetallic connection.
Other methods may be used as alternatives to bonding, such as the ThinPak technique in which contact is made with the chip surface via solder applied over holes in a ceramic plate.
In MPIPPS (Metal Posts Interconnected Parallel Plate Structures), the contacts are made by means of soldered copper posts.
Another method for making contact is via solder bumps in flip-chip technology. This method additionally facilitates improved heat dissipation, since the power semiconductors can be soldered onto DCB substrates on the upper and lower face (DCB stands for Direct Copper Bonding).
It is also possible for contact to be made over a large area via vapor-deposited Cu leads, wherein the conducting-track insulation (Power Module Overlay Structure) is produced by vapor-phase deposition (CVD technique).
Finally, a method for making contact using a patterned foil via an adhesive or solder process has also been disclosed.
U.S. Pat. No. 5,616,886 contains a proposal for a bondless module, in which no process details are specified.
In Ozmat B., Korman C. S. and Filion R.: “An Advanced Approach to Power Module Packaging”, 0-7803-6437-6/00, IEEE, 2000 a method is disclosed whereby power semiconductors are applied to a film that is stretched in a frame.
In Ostmann A., Neumann A.: “Chip in Polymer—the Next Step in Miniaturization”, in “Advancing Microelectronics”, Volume 29, No. 3, May/June 2002, a method is disclosed whereby logic chips located on a substrate are embedded in a polymer.